The present invention relates to a high-voltage level shifting circuit with optimized response time.
More particularly, the invention relates to a high-voltage level shifting circuit particularly suitable for use in a switching regulator of the buck converter type, the level shifting circuit being used for the driver of an input power transistor (commonly known as HSIDE).
It is known that the HSIDE input power transistor driver of a switching regulator of the buck converter type requires a circuit, commonly termed high-voltage level shifting, whose task is to reference to two voltages, termed VBOOT and VPHASE, whose difference remains fixed over time, a digital logic signal X referenced to the supply voltage VDD.
The two voltages VBOOT and VPHASE can vary suddenly by tens of volts.
The circuit shown in FIG. 1 illustrates a solution that is currently in use.
The level shifting of the digital signal X occurs by switching on and off a current Idd, and this allows to drive, by means of a resistor R1 the gate terminal of the inverter constituted by the pair of transistors M1 and M2.
The inverter must be sized so as to have the highest possible threshold, since when the voltage VPHASE (which is normally between xe2x88x920.8 V and Vin, where Vin is typically 20 V) is equal to xe2x88x920.8 V and the digital signal X is equal to 1, the voltage Vg at the node that is common to the gate terminals of the transistors M1 and M2 that compose the inverter can drop at the most to the ground value, and this must ensure the presence of a logic 1 on the signal X.
However, this solution has drawbacks.
First of all, the voltage drop across the resistor R1 must be such as to ensure a logic signal 1 on the digital signal X, taking into account all temperature effects and all process variations. This entails oversizing (by at least 100%, which in the case of the implemented circuit corresponds to 1.5 V) such drop in typical conditions.
This has an effect on the off time of the signal X, i.e., when X passes from 1 to 0, since the drop across the resistor R1 must decrease from the voltage drop determined by the product of the value of the resistor R1 and the value of the current Idd to the tripping value, through a transient characterized by the time constant determined by the product of the value of the resistor R1 and the sum of the value of the parasitic capacitor Cr (parasitic capacitance of the resistor R1) and of the parasitic capacitor Cp (parasitic capacitance of the high-voltage power transistor, MHV).
When the signal X is equal to 0, if the two voltages VBOOT and VPHASE rise suddenly (for example up to 20 V in 24 ns), in many practical applications the value of the parasitic capacitor Cp is such as to keep low the voltage Vg, to the point of switching on the clamp transistor M3. In this case, the output X is, for a certain time, at an incorrect logic value 1, and this time must be subsequently eliminated with a time-constant filter equal to the time for which the output X is at the incorrect logic value 1.
The time determined above is the time that the transient caused by the time constant determined by the product of the sum of the values of the above cited parasitic capacitors and the value of the resistor R1 requires in order to return the voltage across the resistor R1 from approximately VDD to the tripping threshold of the inverter formed by the pair of transistors M1 and M2.
The aim of the present invention is to provide a high-voltage level shifting circuit with optimized response time, in which the time for which the output X is at an incorrect digital value can be reduced simply by ensuring that the drop on the resistor R1 is reduced to a value that is just sufficient to ensure a logic 1 on the digital signal X.
Within this aim, an object of the present invention is to provide a high-voltage level shifting circuit in which the output of the circuit is not at an incorrect logic value 1 for a preset time.
Another object of the present invention is to provide a high-voltage level shifting circuit requiring filters for time constants that are optimized and reduced with respect to the filters currently used in level shifting circuits.
Another object of the present invention is to provide a high-voltage level shifting circuit that requires, like circuits of the known kind, an oversizing of the voltage drop across the resistor R1.
Another object of the present invention is to provide a high-voltage level shifting circuit that is highly reliable, relatively simple to manufacture and at competitive costs.
This aim and these and other objects that will become better apparent hereinafter are achieved by a high-voltage level shifting circuit with optimized response time, comprising: an inverter having an input and an output, the inverter being connected between a first voltage and a second voltage whose difference remains constant over time; a resistor, in which one terminal is connected to said first voltage and a second terminal is connected to an input of said inverter; a high-voltage transistor, which is connected between said second terminal of said resistor and a current source whose switching on and off determine a level shifting of a digital signal; and a clamp transistor, which is connected between said first voltage and a node that is common to said resistor and to said high-voltage transistor; characterized in that the gate terminal of said clamp transistor is connected to the output of said inverter.